1. Field of the Invention
Embodiments of the present invention relate to semiconductor testing.
2. Description of the Related Art
Testing is an important step in the production of semiconductor devices for use. Typically, partially or fully completed semiconductor devices may be tested by bringing terminals disposed on an upper surface of a device to be tested—also referred to as a device under test (or DUT)—into contact with resilient contact elements, for example, as contained in a probe card assembly, as part of a test system. A test system controller may be coupled to the probe card assembly to send and receive test signals to and from the DUTs over a set of test channels. A test system controller with increased test channels can be a significant cost factor for a test system. Test system controllers have evolved to increase the number of channels and hence the number of devices that can be tested in parallel (sometimes referred to as multi-site testing).
During testing, some test channels provide inputs to input pins of the DUTs, others test channels monitor for outputs from output pins of the DUTs, and still others provide inputs to and monitor for outputs from input/output (IO) pins of the DUTs. When a test channel detects an output produced by a DUT, the test channel can compare the output with an expected output. For a functional DUT, the output matches the expected output. If the output from a pin of a DUT does not match the expected output, the test channel can generate an indication of a failure for that pin of that DUT. The failure indication can then be stored in a memory (“failure memory”). In this manner, the failure memory can store one or more failure indications for various pins of various DUTs during testing. The memory can be accessed by the test system controller (e.g., a host computer) to detect which DUTs have failures.
A test may include a plurality of test cycles, each of which includes providing input signals to the DUTs and monitoring for output signals from the DUTs. If a pin on a DUT fails on a test cycle, the pin may continue to fail on subsequent test cycles. The more test cycles in the test, the more failures detected and stored in the failure memory. In some cases, if a pin continues to fail for each test cycle, the failure memory may not be large enough to store all of the corresponding failure indications for that pin (i.e., the memory will overflow). Further, the failure memory may be filled with failure indications for one DUT pin and have no room for failure indications subsequently generated by other DUT pins. Thus, overflow of the failure memory may lead to some defective DUTs escaping detection during the test. In case of failure memory overflow, a test engineer can disable the failing DUT and re-run the test. This may lead to further failure memory overflows, requiring several iterations of the same test, increasing test time, and increasing test cost.
Accordingly, there exists a need in the art for a method and apparatus for testing semiconductor devices that attempts to overcome at least some of the aforementioned deficiencies.